1. Field of the Invention
The present invention generally relates to a method for aligning a wafer stack. In particular, the present invention is directed to a method for aligning a wafer stack for the detection of the relative position of multiple objects by optimizing an adjustable current path.
2. Description of the Prior Art
Lithographic technologies are key technologies that affect the critical dimensions in semiconductor processes. Generally speaking, electric circuit patterns are formed by first transferring the patterns from a photo mask to a photoresist layer in a lithographic process, and then transferring the patterns from the photoresist layer to an underlying material layer such as a dielectric layer or a metal layer in a subsequent etching process. Thus, several marks are required to be disposed on the wafer or the underlying material layers to increase alignment accuracy between layers.
In order to increase production yield, alignment and overlay marks are typically provided on a wafer or material layers. By way of example, a sample wafer with alignment marks is put into product lines for testing alignment accuracy before wafers are practically in mass production. In the lithography process, the photo mask and the wafer are first aligned by an exposure tool using a set of pre-layer alignment marks and current-layer alignment marks typically located near an edge or on a scribe line of the wafer surface. Then, the exposure tool detects the pre-layer alignment marks and current-layer alignment marks and the reflected light signal is analyzed by the exposure tool to obtain the required precise alignment prior to the actual exposure process. The alignment marks typically includes a set of trenches which are etched into a material layer on a wafer.
On one hand, “pre-layer” may refer to a material layer or a wafer processed in a previous step. On the other hand, “current-layer” may refer to another material layer or another wafer which is to be processed in the current process.
After exposure, the photoresist layer on the wafer is then subjected to development process to form a photoresist pattern. Before implementing the etching process for transferring the photoresist pattern into the underlying material layer, it is important to check if the electric circuit features which are defined in the developed photoresist layer perfectly match with the electric circuit patterns which are previously formed on the wafer; otherwise, the previously formed electric circuit may fail. Therefore, accuracy of the alignment has to be checked. Then, offset distances between the pre-layer mark and the current-layer mark can be measured by a tool, and the exposure parameters and development parameters can be adjusted.
However, the above-described prior art has some fatal applicable drawbacks. First, since the alignment mark or the overlay mark is detected by devices such as an exposure tool or an overlay tool, the alignment mark or the overlay mark therefore are sort of “optical marks” and they must be large enough or plenty enough to be practical. As known in this art, the surface of a wafer is getting more and more scarce due to the demanding shrinkage of the critical dimension of the semiconductor elements so there is less and less space left for the over-sized alignment marks or the overlay marks.
Second, since the alignment marks and the overlay marks are optical marks, they can only be useful in transparent or semi-transparent conditions. Moreover, supposing there are too many layers stacking on one another, as a result, both the alignment marks and the overlay marks become too weak to be detected, in particular, when the substrates or the layers to be aligned with one another are not transparent at all, i.e. opaque. Accordingly, a novel alignment mark or overlay mark is still needed to overcome these restrictive problems.